Smart in-chip liquid cooling for advanced microelectronic systems

Solutions developed

UniScool proposes a new patented and highly innovative liquid cooling system, based on an adaptive heat sink that includes a series of thermally activated fins capable of efficiently adapting the local heat extraction to time-dependent and non-uniform heat load scenarios, providing high-temperature uniformity without a custom design stage, avoiding overcooling and reducing the required pumping power, what provides an added-value solution that improves the existing ones. But with this project, we aim to go further and enter a new leading thermal management paradigm by developing an embedded liquid cooling system at the chip stack with the advantages of self-adaptive fins. This solution can boost the heat extraction capacity of the system up to more than 1kW/cm2 with significantly reduced flow rate and pumping power consumption (x 0.5) high performance, and significantly reduced space (x10) in a sustainable and environmentally friendly way.

With Women TechEU, we aim to do a prototype demonstration of in-chip liquid cooling, embedded at the chip stack, based on a microchannel array with self-adaptive fins that regulate the local thermal resistance according to local temperature, which can be an open door for semiconductor manufacturers to believe in in-chip cooling and incorporate UniSCool solution in their microelectronic components.

Main results

The continuous increase in power density of integrated circuits due to the ever-increasing rate of data and communications and the constant push for size and cost reduction settles thermal management as a big concern for the ICT industry. Consequently, cooling, with its enormous consumption of electricity and water has an increasingly large environmental impact, and new technologies to extract the heat in a more sustainable way are committed. A promising approach for more efficient thermal management is to directly embed liquid cooling inside the chip, eliminating the thermal resistance between the semiconductor die and the packaging.